22
LT1576/LT1576-5
APPLICATIONS INFORMATION
WUU
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I check switching regulator loop stability by pulse loading
the regulator output while observing transient response at
the output, using the circuit shown in Figure 13. The
regulator loop is “hit” with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This
causes the output to jump a few millivolts, then settle back
to the original value, as shown in Figure 14. A well behaved
loop will settle back cleanly, whereas a loop with poor
phase or gain margin will “ring” as it settles. The
number
of rings indicates the degree of stability, and the
frequency
of the ringing shows the approximate unity-gain fre-
quency of the loop.
Amplitude
of the signal is not particu-
larly important, as long as the amplitude is not so high that
the loop behaves nonlinearly.
How Do I Test Loop Stability?
The “standard” compensation for LT1576 is a 100pF
capacitor for C
C
, with R
C
= 0Ω. While this compensation
will work for most applications, the “optimum” value for
loop compensation components depends, to various ex-
tent, on parameters which are not well controlled. These
include
inductor value
(±30% due to production toler-
ance, load current and ripple current variations),
output
capacitance
(±20% to ±50% due to production tolerance,
temperature, aging and changes at the load),
output
capacitor ESR
(±200% due to production tolerance, tem-
perature and aging), and finally,
DC input voltage and
output load current
. This makes it important for the
designer to check out the final design to ensure that it is
“robust” and tolerant of all these variations.
0.2ms/DIV 1576 F14
10mV/DIV
V
OUT
AT
I
OUT
= 500mA
BEFORE FILTER
V
OUT
AT
I
OUT
= 500mA
AFTER FILTER
LOAD PULSE
THROUGH 50Ω
f ≈ 780Hz
5A/DIV
V
OUT
AT
I
OUT
= 50mA
AFTER FILTER
Figure 14. Loop Stability Check
TO
OSCILLOSCOPE
SYNC
ADJUSTABLE
DC LOAD
ADJUSTABLE
INPUT SUPPLY
100Hz TO 1kHz
100mV TO 1V
P-P
100µF TO
1000µF
RIPPLE FILTER
1576 F13
TO X1
OSCILLOSCOPE
PROBE
3300pF 330pF
50Ω
470Ω
4.7k
SWITCHING
REGULATOR
+
Figure 13. Loop Stability Test Circuit
