LMX2486
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SNAS324 –JANUARY 2006
R7 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data[19:0] C3 C2 C1 C0
R7 0 0 0 0 0 0 0 0 0 0 DI 0 1 0 0 0 IF_ RF IF_ RF 1 1 1 1
V4 RS _R CP _C
T ST T PT
DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked
condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison
frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4.
This enables this circuitry to work at higher comparison frequencies. It is recommended that this bit be enabled
whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.
IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a TRI-STATE
condition. This feature should be disabled for normal operation. Note that a counter reset is applied whenever the
chip is powered up via software or CE pin.
IF_RST IF PLL N and R Counters IF PLL Charge Pump
0 (Default) Normal Operation Normal Operation
1 Counter Reset TRI-STATE
RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a TRI-STATE
condition. This feature should be disabled for normal operation. This feature should be disabled for normal
operation. Note that a counter reset is applied whenever the chip is powered up via software or CE pin.
RF_RST RF PLL N and R Counters RF PLL Charge Pump
0 (Default) Normal Operation Normal Operation
1 Counter Reset TRI-STATE
RF_TRI -- RF Charge Pump TRI-STATE
When this bit is enabled, the RF PLL charge pump is put in a TRI-STATE condition, but the counters are not
reset. This feature is typically disabled for normal operation.
RF_TRI RF PLL N and R Counters RF PLL Charge Pump
0 (Default) Normal Operation Normal Operation
1 Normal Operation TRI-STATE
IF_TRI -- IF Charge Pump TRI-STATE
When this bit is enabled, the IF PLL charge pump is put in a TRI-STATE condition, but the counters are not
reset. This feature is typically disabled for normal operation.
IF_TRI IF PLL N and R Counters IF PLL Charge Pump
0 (Default) Normal Operation Normal Operation
1 Normal Operation TRI-STATE
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