LMX2486
SNAS324 –JANUARY 2006
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RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the
FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and
the FLoutRF pin operates as a general purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value
between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is utilized as the RF Fastlock
output pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase
detector comparison cycles the RF synthesizer will spend in the Fastlock state.
RF_TOC Fastlock Mode Fastlock Period [CP events] FLoutRF Pin Functionality
0 Disabled N/A High Impedance
1 Manual N/A Logic “0” State.
Forces all Fastlock conditions
2 Disabled N/A Logic “0” State
3 Disabled N/A Logic “1” State
4 Enabled 4X2 = 8 Fastlock
5 Enabled 5X2 = 10 Fastlock
… Enabled … Fastlock
16383 Enabled 16383X2 = 32766 Fastlock
RF_CPF -- RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL. Note that the Fastlock charge
pump current, steady state current, and CSR control are all interrelated.
RF_CPF RF Charge Pump State Typical RF Charge Pump Current at 3
Volts (µA)
0 1X 95
1 2X 190
2 3X 285
3 4X 380
4 5X 475
5 6X 570
6 7X 665
7 8X 760
8 9X 855
9 10X 950
10 11X 1045
11 12X 1140
12 13X 1235
13 14X 1330
14 15X 1425
15 16X 1520
CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence
of phase detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control
are all interrelated. Refer to CYCLE SLIP REDUCTION AND FASTLOCK for information on how to use this.
CSR CSR State Sample Rate Reduction Factor
0 Disabled 1
1 Enabled 1/2
2 Enabled 1/4
3 Enabled 1/16
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