LMX2486
SNAS324 –JANUARY 2006
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DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional
spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific.
Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero,
dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often
occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends
not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is
decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.
DITH Dithering Mode Used
0 Disabled
1 Weak Dithering
2 Strong Dithering
3 Reserved
ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0
register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case
is when the CE pin is low. In this case, the ATPU function is disabled.
R5 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[19:0] C3 C2 C1 C0
R5 RF_FD[21:12] RF_FN[21:12] 1 0 1 1
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