LMX2486
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SNAS324 –JANUARY 2006
IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P IF Prescaler Maximum Frequency
0 8/9 2300 MHz
1 16/17 3000 MHz
RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP RF Charge Pump Polarity
0 Negative
1 Positive (Default)
IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a
negative phase detector polarity.
IF_CPP IF Charge Pump Polarity
0 Negative
1 Positive
OSC_OUT Oscillator Output Buffer Enable
OSC_OUT OSCout Pin
0 Disabled (High Impedance)
1 Buffered output of OSCin pin
OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF
R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency
presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.
OSC2X Frequency Presented to RF R Counter Frequency Presented to IF R Counter
0 f
OSCin
f
OSCin
1 2 x f
OSCin
FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels
closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the
loop filter should be at least one greater than the order of the delta-sigma modulator in order to allow for
sufficient roll-off.
FM Function
0 Fractional PLL mode with a 4th order delta-sigma modulator
1 Disable the delta-sigma modulator. Recommended for test use only.
2 Fractional PLL mode with a 2nd order delta-sigma modulator
3 Fractional PLL mode with a 3rd order delta-sigma modulator
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