LMX2486
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SNAS324 –JANUARY 2006
This corresponds to the following bit settings.
Register Bit Location Bit Name Bit Description Bit Value Bit State
R4[23] ATPU Autopowerup 0 Disabled
R4[17:16] DITH Dithering 2 Strong
R4[15:14] FM Modulator Order 3 3rd Order
R4[12] OSC_2X Oscillator Doubler 0 Disabled
R4[11] OSC_OUT OSCout Pin Enable 0 Disabled
R4
IF Charge Pump
R4[10] IF_CPP 1 Positive
Polarity
RF Charge Pump
R4[9] RF_CPP 1 Positive
Polarity
R4[8] IF_P IF PLL Prescaler 1 16/17
R4[7:4] MUX Ftest/LD Output 0 Disabled
Extended Fractional
R5[23:14] RF_FD[21:12] 0 Disabled
Denominator
R5
Extended Fractional
R5[13:4] RF_FN[21:12] 0 Disabled
Numerator
R6[23:22] CSR Cycle Slip Reduction 0 Disabled
Fastlock Charge
R6 R6[21:18] RF_CPF 0 Disabled
Pump Current
R6[17:4] RF_TOC RF Timeout Counter 0 Disabled
Lock Detect Disabled (Fcomp ≤
R7[13] DIV4 0
Adjustment 20 MHz)
R7[7] IF_RST IF PLL Counter Reset 0 Disabled
R7 RF PLL Counter
R7[6] RF_RST 0 Disabled
Reset
R7[5] IF_CPT IF PLL TRI-STATE 0 Disabled
R7[4] RF_CPT RF PLL TRI-STATE 0 Disabled
R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[19:0] C3 C2 C1 C0
OS RF
OS IF_
AT DITH FM C_ _ IF_ MUX
R4 0 1 0 0 0 0 C_ CP 1 0 0 1
PU [1:0] [1:0] OU CP P [3:0]
2X P
T P
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