LMX2486
www.ti.com
SNAS324 –JANUARY 2006
IF_N[18:0] -- IF N Divider Value
Table 3. IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N Value
IF_B IF_A
≤23 N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
24-55 Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
56 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
57 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1
... . . . . . . . . . . . . . . . . . . .
262143 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
Table 4. Operation with the 16/17 Prescaler (IF_P=1)
N Value IF_B IF_A
≤47 N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48-239 Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
241 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1
... . . . . . . . . . . . . . . . . . . .
524287 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
R3 REGISTER
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[19:0] C3 C2 C1 C0
R3 ACCESS[3:0] RF_CPG[3:0] IF_R[11:0] 0 1 1 1
IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for
IF_R is 3.
R Value IF_R[11:0]
3 0 0 0 0 0 0 0 0 0 0 1 1
... . . . . . . . . . . . .
4095 1 1 1 1 1 1 1 1 1 1 1 1
Copyright © 2006, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LMX2486
