LMX2486
www.ti.com
SNAS324 –JANUARY 2006
NOTE
For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction,
Fastlock, and many other topics, visit http://www.ti.com. Here there is the EasyPLL
simulation tool and an online reference called "PLL Performance, Simulation, and Design",
by Dean Banerjee.
Programming Description
GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program
the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown below. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data
stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted
in MSB first. Note that it is best to program the N counter last, since doing so initializes the digital lock detector
and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT program values into
these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the
R7 register.
MSB LSB
DATA [21:0] CTL [3:0]
23 4 3 2 1 0
Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are
mapped to the target control register.
C3 C2 C1 C0 DATA Location
x x x 0 R0
0 0 1 1 R1
0 1 0 1 R2
0 1 1 1 R3
1 0 0 1 R4
1 0 1 1 R5
1 1 0 1 R6
1 1 1 1 R7
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