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LMX2486

LMX2486首页预览图
型号: LMX2486
PDF文件:
  • LMX2486 PDF文件
  • LMX2486 PDF在线浏览
功能描述: 1.0 GHz - 4.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL
PDF文件大小: 1180.69 Kbytes
PDF页数: 共40页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LMX2486
PDF页面索引
120%
LMX2486
SNAS324 JANUARY 2006
www.ti.com
K Loop Bandwidth R2p Value Lock Time
1 1.00 X Open 100 %
2 1.41 X R2/0.41 71 %
3 1.73 X R2/0.73 58%
4 2.00 X R2 50%
8 2.83 X R2/1.83 35%
9 3.00 X R2/2 33%
16 4.00 X R2/3 25%
The above table shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the
ratio , K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally
recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means
that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it
would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep
the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but
not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation
tools, or trial and error.
Capacitor Dielectric Considerations for Lock Time
The LMX2486 has a high fractional modulus and high charge pump gain for the lowest possible phase noise.
One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop
filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor
dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock
times, where as using X7R or Z5R capacitors can increase lock time by 0 500%. However, it is a general
tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor
dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances,
allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase
noise and spurs.
FRACTIONAL SPUR AND PHASE NOISE CONTROLS
Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be
made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at
increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than
the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional
spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The
bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.
The first step to do is choose FM, for the delta sigma modulator order. It is recommended to start with FM = 3 for
a third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-
fractional spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary
fractional spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order),
typically gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd
order modulator is a compromise.
The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs,
but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or
even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but
the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best).
Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them
completely, but adds the most phase noise. Weak dithering (DITH = 1) is a compromise.
The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same,
expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the
fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional
denominator as large as possible, but not to exceed 4095, so it is not necessary to use the extended fractional
numerator or denominator.
22 Submit Documentation Feedback Copyright © 2006, Texas Instruments Incorporated
Product Folder Links: LMX2486
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