LMX2486
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SNAS324 –JANUARY 2006
Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the
same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases
where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can
occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically
the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR
provides no benefit. There is a glitch when CSR is disengaged, but since CSR should be disengaged long before
the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at
the peak time of the transient response. Because this time is typically much sooner than Fastlock should be
disengaged, it does not make sense to use CSR and Fastlock in combination.
Fastlock
Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the
comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can
offer. Since Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a
significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually provide
an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The
reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits
the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option
of reducing the comparison frequency at the expense of phase noise in order to satisfy this constraint on
comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these
circumstances. When using Fastlock, it is also recommended that the steady state charge pump state be 4X or
less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher
order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well
optimized when the higher charge pump current and Fastlock resistor are engaged.
Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available
factors are 1/2, 1/4, and 1/16. In order to preserve the same loop characteristics, it is recommended that the
following constraint be satisfied:
(Fastlock Charge Pump Current) / (Steady State Charge Pump Current) = CSR
In order to satisfy this constraint, the maximum charge pump current in steady state is 8X for a CSR of 1/2, 4X
for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump
currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger
than this will not improve lock time, and will result in worse phase noise.
Consider an example where the desired loop bandwidth in steady state is 100 kHz and the comparison
frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it
was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is
probably sufficient. A charge pump current of 8X could be used in steady state, and a factor of 16X could be
used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies
the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the
time, since it would probably have better phase noise, and the degradation in lock time would not be too severe.
Using Fastlock to Improve Lock Times
Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed in order to determine
the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel
during Fastlock. This ratio is calculated as follows:
K = ( Fastlock Charge Pump Current ) / ( Steady State Charge Pump Current )
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