Address Reg. Bits Description Default
0x10h P [7:4] Control compensation gain for Mic2 channel at ALL frequencies (Note 1)
0000 (0) –3.0dB
0000
0001 (1) –3.0dB
0010 (2) –2.5dB
0011 (3) –2.0dB
0100 (4) –1.5dB
0101 (5) –1.0dB
0110 (6) –0.5dB
0111 (7) 0.0dB
1000 (8) 0.0dB
1001 (9) 0.5dB
1010 (A) 1.0dB
1011 (B) 1.5dB
1100 (C) 2.0dB
1101 (D) 2.5dB
1110 (E) 3.0dB
1111 (F) 3.0dB
[3:0] Control compensation gain for Mic1 channel at ALL frequencies (Note 1)
0000 (0) –3.0dB
0000
0001 (1) –3.0dB
0010 (2) –2.5dB
0011 (3) –2.0dB
0100 (4) –1.5dB
0101 (5) –1.0dB
0110 (6) –0.5dB
0111 (7) 0.0dB
1000 (8) 0.0dB
1001 (9) 0.5dB
1010 (A) 1.0dB
1011 (B) 1.5dB
1100 (C) 2.0dB
1101 (D) 2.5dB
1110 (E) 3.0dB
1111 (F) 3.0dB
0x11h Q [6:0] Values are clocked into EEPROM registers once “newdata” pulse is generated
[7]
StoreBar signal
storeBar = 0 enables EEPROM programming
storeBar = 1 data clock into EEPROM registers
1
0x12h R [0] Start Calibration via I2C ‘0’ to ‘1’ = start calibration (keep ‘1’ during calibration) 0
[7] Internal test
000000
0
( ) represents binary value in hexadecimal format
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LMV1088
