18.3 ADC REGISTERS
ADC_RESTART: ADC Restart Conversion (Address 0x0B)
Bit Bit Symbol Bit Description
[7:1] Reserved -
0 RESTART
Restart conversion
1: Restart conversion.
14.2.1. ADC_AUXCN: ADC Auxiliary Control (Address 0x12)
Bit Bit Symbol Bit Description
7 Reserved -
6 RESET_SYSCAL
The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are:
0 (default): preserved even when "REG_AND_CNV_ RST" = 0xC3.
1: reset by setting "REG_AND_CNV_ RST" = 0xC3.
5 CLK_EXT_DET
External clock detection
0 (default): "External Clock Detection" is operational
1: "External-Clock Detection" is bypassed
4 CLK_SEL
Clock select – only valid if CLK_EXT_DET = 1
0 (default): Selects internal clock
1: Selects external clock
[3:0]
RTD_CUR_SEL
(LMP90100 and LMP90098
only)
Selects RTD Current as follows:
0x0 (default): 0 µA
0x1: 100 µA
0x2: 200 µA
0x3: 300 µA
0x4: 400 µA
0x5: 500 µA
0x6: 600 µA
0x7: 700 µA
0x8: 800 µA
0x9: 900 µA
0xA: 1000 µA
ADC_DONE: ADC Data Available (Address 0x18)
Bit Bit Symbol Bit Description
[7:0] DT_AVAIL_B
Data Available – indicates if new conversion data is available
0x00 − 0xFE: Available
0xFF: Not available
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LMP90100/LMP90099/LMP90098/LMP90097
