16.5.4 CSB - Chip Select Bar
An SPI transaction begins when the master asserts (active
low) CSB and ends when the master deasserts (active high)
CSB. Each transaction might be separated by a subsequent
one with a CSB deassertion, but this is optional. Once CSB
is asserted, it must not pulse (deassert and assert again) dur-
ing a (desired) transaction.
CSB can be grounded in systems where LMP90xxx is the only
SPI slave. This frees the software from handling the CSB.
Care has to be taken to avoid any false edge on SCLK, and
while operating in this mode, the streaming transaction should
not be used because exiting from this mode can only be done
through a CSB deassertion.
16.5.5 SPI Reset
SPI Reset resets the SPI-Protocol State Machine by moni-
toring the SDI for at least 73 consecutive 1's at each SCLK
rising edge. After an SPI Reset, SDI is monitored for a pos-
sible Write Instruction at each SCLK rising edge.
SPI Reset will reset the Upper Address Register (URA) to 0,
but the register contents are not reset.
By default, SPI reset is disabled, but it can be enabled by
writing 0x01 to SPI Reset Register (ADDR 0x02).
16.5.6 DRDYB - Data Ready Bar
DRDYB is a signal generated by the LMP90xxx that indicates
a fresh conversion data is available in the ADC_DOUT reg-
isters.
DRDYB is automatically asserted every (1/ODR) second and
deasserts when ADC_DOUT is completely read out (LSB of
ADC_DOUTL) ().
30139584
FIGURE 20. DRDYB Behavior for a Complete ADC_DOUT Reading
If ADC_DOUT is not completely read out (Figure 21) or is not
read out at all, but a new ADC_DOUT is available, then
DRDYB will automatically pulse for t
DRDYB
second. The value
for t
DRDYB
can be found in Section 13.0 Timing Diagrams.
30139585
FIGURE 21. DRDYB Behavior for an ADC_DOUT not Read
If ADC_DOUT is being read, while the new ADC_DOUT be-
comes available, then the ADC_DOUT that is being read is
still valid(Figure 22). DRDYB will be deasserted at the LSB of
the data being read, but a consecutive read on the
ADC_DOUT register will fetch the newly converted data avail-
able.
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