REF LEVEL
0.000 dB
0.0 deg
100 1k
START 50.000 Hz
10k
STOP 50 000.000 Hz
/DIV
10.000 dB
45.000 deg
0
GAIN
PHASE
REF LEVEL
0.000 dB
0.0 deg
100 1k
START 50.000 Hz
10k
STOP 50 000.000 Hz
/DIV
10.000 dB
45.000 deg
0
GAIN
PHASE
LM5005
SNVS397D –SEPTEMBER 2005–REVISED MARCH 2013
www.ti.com
Figure 18. Error Amplifier Gain and Phase
The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.
Figure 19. Overall Loop Gain and Phase
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response.
C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value
of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer
function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of
the pole added by C6 is: f
p2
= fz x C5 / C6. An alternative method to decrease the error amplifer noise
susceptibility is to connect a capacitor from the COMP pin to the AGND pin. When using this method the value of
the capacitor should not exceed 100pF.
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5005
