Figure 13-9. Master Burst SEND ........................................................................................... 336
Figure 13-10. Master Burst RECEIVE ...................................................................................... 337
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 338
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 339
Figure 13-13. Slave Command Sequence ................................................................................ 340
Figure 14-1. CAN Controller Block Diagram ............................................................................ 365
Figure 14-2. CAN Data/Remote Frame .................................................................................. 366
Figure 14-3. Message Objects in a FIFO Buffer ...................................................................... 374
Figure 14-4. CAN Bit Time .................................................................................................... 378
Figure 15-1. Ethernet Controller ............................................................................................. 413
Figure 15-2. Ethernet Controller Block Diagram ...................................................................... 413
Figure 15-3. Ethernet Frame ................................................................................................. 414
Figure 15-4. Interface to an Ethernet Jack .............................................................................. 419
Figure 16-1. 100-Pin LQFP Package Pin Diagram .................................................................. 459
Figure 16-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 460
Figure 19-1. Load Conditions ................................................................................................ 488
Figure 19-2. JTAG Test Clock Input Timing ............................................................................. 490
Figure 19-3. JTAG Test Access Port (TAP) Timing .................................................................. 491
Figure 19-4. JTAG TRST Timing ............................................................................................ 491
Figure 19-5. External Reset Timing (RST) .............................................................................. 492
Figure 19-6. Power-On Reset Timing ..................................................................................... 492
Figure 19-7. Brown-Out Reset Timing .................................................................................... 492
Figure 19-8. Software Reset Timing ....................................................................................... 492
Figure 19-9. Watchdog Reset Timing ..................................................................................... 493
Figure 19-10. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 494
Figure 19-11. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 494
Figure 19-12. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 495
Figure 19-13. I
2
C Timing ......................................................................................................... 496
Figure 19-14. External XTLP Oscillator Characteristics ............................................................. 498
Figure D-1. 100-Pin LQFP Package ...................................................................................... 522
Figure D-2. 108-Ball BGA Package ...................................................................................... 524
9June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller