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LM3S8530-IQR80-C1

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型号: LM3S8530-IQR80-C1
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  • LM3S8530-IQR80-C1 PDF文件
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功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
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120%
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 6-5, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 6-5. RCC2 Fields that Override RCC fields
Overrides RCC FieldRCC2 Field...
SYSDIV, bits[26:23]SYSDIV2, bits[28:23]
PWRDN, bit[13]PWRDN2, bit[13]
BYPASS, bit[11]BYPASS2, bit[11]
OSCSRC, bits[5:4]OSCSRC2, bits[6:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x0780.2810
16171819202122232425262728293031
reservedSYSDIV2reservedUSERCC2
ROROROROROROROR/WR/WR/WR/WR/WR/WROROR/WType
0000000111100000Reset
0123456789101112131415
reservedOSCSRC2reservedBYPASS2
reserved
PWRDN2reserved
ROROROROR/WR/WR/WROROROROR/WROR/WROROType
0000100000010100Reset
DescriptionResetTypeNameBit/Field
Use RCC2
When set, overrides the RCC register fields.
0R/WUSERCC231
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved30:29
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 6-3 on page 70 for programming guidelines.
0x0FR/WSYSDIV228:23
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0ROreserved22:14
Power-Down PLL
When set, powers down the PLL.
1R/WPWRDN213
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved12
June 22, 201088
Texas Instruments-Production Data
System Control
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