Register 7: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
EXTPORBORWDTSWreserved
R/WR/WR/WR/WR/WROROROROROROROROROROROType
-----00000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:5
Software Reset
When set, indicates a software reset is the cause of the reset event.
-R/WSW4
Watchdog Timer Reset
When set, indicates a watchdog reset is the cause of the reset event.
-R/WWDT3
Brown-Out Reset
When set, indicates a brown-out reset is the cause of the reset event.
-R/WBOR2
Power-On Reset
When set, indicates a power-on reset is the cause of the reset event.
-R/WPOR1
External Reset
When set, indicates an external reset (RST assertion) is the cause of
the reset event.
-R/WEXT0
83June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller