Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 6-4. System Control Register Map
See
page
DescriptionResetTypeNameOffset
76Device Identification 0-RODID00x000
91Device Identification 1-RODID10x004
93Device Capabilities 00x00FF.002FRODC00x008
94Device Capabilities 10x0700.309FRODC10x010
96Device Capabilities 20x000F.1031RODC20x014
98Device Capabilities 30x8300.0000RODC30x018
99Device Capabilities 40x5000.007FRODC40x01C
78Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030
79LDO Power Control0x0000.0000R/WLDOPCTL0x034
119Software Reset Control 00x00000000R/WSRCR00x040
120Software Reset Control 10x00000000R/WSRCR10x044
122Software Reset Control 20x00000000R/WSRCR20x048
80Raw Interrupt Status0x0000.0000RORIS0x050
81Interrupt Mask Control0x0000.0000R/WIMC0x054
82Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058
83Reset Cause-R/WRESC0x05C
84Run-Mode Clock Configuration0x0780.3AD1R/WRCC0x060
87XTAL to PLL Translation-ROPLLCFG0x064
88Run-Mode Clock Configuration 20x0780.2810R/WRCC20x070
101Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100
107Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104
113Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108
103Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110
109Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114
115Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118
105Deep Sleep Mode Clock Gating Control Register 00x00000040R/WDCGC00x120
111Deep Sleep Mode Clock Gating Control Register 10x00000000R/WDCGC10x124
117Deep Sleep Mode Clock Gating Control Register 20x00000000R/WDCGC20x128
90Deep Sleep Clock Configuration0x0780.0000R/WDSLPCLKCFG0x144
June 22, 201074
Texas Instruments-Production Data
System Control