Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
StellarisWare Parameter
a
Frequency (BYPASS2=1)Frequency
(BYPASS2=0)
DivisorSYSDIV2
SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x05
SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x06
SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x07
SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x08
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09
...............
SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
6.1.4.3 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 84) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.1.4.4 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency, and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 87). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 19-8 on page 488 shows the actual PLL frequency and error for
a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 84)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
6.1.4.5 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 84 and page 88).
71June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
