■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 6-5 on page 69 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled.
Figure 6-5. Main Clock Tree
PLL
(400 MHz)
Main OSC
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
÷ 4
Hibernation
Module
(32.768 kHz)
÷ 25
PWRDN
ADC Clock
System Clock
XTAL
a
PWRDN
b
MOSCDIS
a
IOSCDIS
a
OSCSRC
b,d
BYPASS
b,d
SYSDIV
b,d
USESYSDIV
a,d
PWMDW
a
USEPWMDIV
a
PWM Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
÷ 2
÷ 50 CAN Clock
Note: The figure above shows all features available on all Stellaris® Fury-class devices.
69June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller