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LM3S8530-IQR80-C1

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型号: LM3S8530-IQR80-C1
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功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
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制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
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6.1.4 Clock Control
System control determines the control of clocks in this part.
6.1.4.1 Fundamental Clock Sources
There are multiple clock sources for use in the device:
Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require
the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%.
Applications that do not depend on accurate clock sources may use this clock source to reduce
system cost. The internal oscillator is the clock source the device uses during and following POR.
If the main oscillator is required, software must enable the main oscillator following reset and
allow the main oscillator to stabilize before changing the clock reference.
Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC
through the specified speed of the device. The supported crystals are listed in the XTAL bit field
in the RCC register (see page 84).
Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator,
except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during
Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal
switching and also allows the main oscillator to be powered down.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 6-1 on page 68 shows how the various clock sources can be used in a system.
Table 6-1. Clock Source Options
Used as SysClk?Drive PLL?Clock Source
BYPASS = 1, OSCSRC = 0x1YesBYPASS = 1NoInternal Oscillator (12 MHz)
BYPASS = 1, OSCSRC = 0x2YesBYPASS = 1NoInternal Oscillator divide by 4 (3
MHz)
BYPASS = 1, OSCSRC = 0x0YesBYPASS = 0, OSCSRC =
0x0
YesMain Oscillator
BYPASS = 1, OSCSRC = 0x3YesBYPASS = 1NoInternal 30-kHz Oscillator
6.1.4.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
Source of clocks in sleep and deep-sleep modes
June 22, 201068
Texas Instruments-Production Data
System Control
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