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LM3S8530-IQR80-C1

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型号: LM3S8530-IQR80-C1
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  • LM3S8530-IQR80-C1 PDF文件
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功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
PDF页面索引
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120%
5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially
into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Stellaris
®
JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris
®
JTAG instructions select the Stellaris
®
TDO
outputs. The multiplexer is controlled by the Stellaris
®
JTAG controller, which has comprehensive
programming for the ARM, Stellaris
®
, and unimplemented JTAG instructions.
The Stellaris
®
JTAG module has the following features:
IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
Four-bit Instruction Register (IR) chain for storing JTAG instructions
IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
ARM additional instructions: APACC, DPACC and ABORT
Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
51June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
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