Table 17-5. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
GPIO port E bit 3.TTLI/OPE3A12
SSI module 1 transmit.TTLOSSI1Tx
No connect. Leave the pin electrically unconnected/isolated.--NCB1
No connect. Leave the pin electrically unconnected/isolated.--NCB2
No connect. Leave the pin electrically unconnected/isolated.--NCB3
No connect. Leave the pin electrically unconnected/isolated.--NCB4
The ground reference for the analog circuits ( etc.). These are
separated from GND to minimize the electrical noise contained on
VDD from affecting the analog functions.
Power-GNDAB5
Ground reference for logic and I/O pins.Power-GNDB6
GPIO port B bit 5.TTLI/OPB5B7
GPIO port C bit 2.TTLI/OPC2B8
JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1B9
JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLI/OTMS
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1B10
GPIO port E bit 2.TTLI/OPE2B11
SSI module 1 receive.TTLISSI1Rx
GPIO port E bit 1.TTLI/OPE1B12
SSI module 1 frame.TTLI/OSSI1Fss
No connect. Leave the pin electrically unconnected/isolated.--NCC1
No connect. Leave the pin electrically unconnected/isolated.--NCC2
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power-VDD25C3
Ground reference for logic and I/O pins.Power-GNDC4
Ground reference for logic and I/O pins.Power-GNDC5
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
Power-VDDAC6
The positive supply (3.3 V) for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be connected to 3.3 V, regardless of
system implementation.
Power-VDDAC7
GND of the Ethernet PHY.Power-GNDPHYC8
GND of the Ethernet PHY.Power-GNDPHYC9
VCC of the Ethernet PHY.Power-VCCPHYC10
GPIO port B bit 2.TTLI/OPB2C11
I
2
C module 0 clock.ODI/OI2C0SCL
GPIO port B bit 3.TTLI/OPB3C12
I
2
C module 0 data.ODI/OI2C0SDA
June 22, 2010472
Texas Instruments-Production Data
Signal Tables
