Table 3-1. Memory Map (continued)
For details on
registers, see
page ...
DescriptionEndStart
384CAN1 Controller0x4004.1FFF0x4004.1000
384CAN2 Controller0x4004.2FFF0x4004.2000
-Reserved0x4004.7FFF0x4004.3000
422Ethernet Controller0x4004.8FFF0x4004.8000
-Reserved0x400F.CFFF0x4004.9000
128Flash control0x400F.DFFF0x400F.D000
75System control0x400F.EFFF0x400F.E000
-Reserved0x41FF.FFFF0x400F.F000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
-
Reserved0xDFFF.FFFF0x4400.0000
Private Peripheral Bus
ARM®
Cortex™-M3
Technical
Reference
Manual
Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
ARM®
Cortex™-M3
Technical
Reference
Manual
Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
ARM®
Cortex™-M3
Technical
Reference
Manual
Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
-Reserved0xE000.DFFF0xE000.3000
ARM®
Cortex™-M3
Technical
Reference
Manual
Nested Vectored Interrupt Controller (NVIC)0xE000.EFFF0xE000.E000
-Reserved0xE003.FFFF0xE000.F000
ARM®
Cortex™-M3
Technical
Reference
Manual
Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
-
Reserved0xFFFF.FFFF0xE004.1000
a. All reserved space returns a bus fault when read or written.
b. The unavailable flash will bus fault throughout this range.
c. The unavailable SRAM will bus fault throughout this range.
47June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller