3 Memory Map
The memory map for the LM3S8530 controller is provided in Table 3-1 on page 46.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Table 3-1. Memory Map
a
For details on
registers, see
page ...
DescriptionEndStart
Memory
128On-chip flash
b
0x0001.7FFF0x0000.0000
-Reserved0x1FFF.FFFF0x0001.8000
128Bit-banded on-chip SRAM
c
0x2000.FFFF0x2000.0000
-Reserved0x21FF.FFFF0x2001.0000
124Bit-band alias of 0x2000.0000 through 0x200F.FFFF0x221F.FFFF0x2200.0000
-
Reserved0x3FFF.FFFF0x2220.0000
FiRM Peripherals
229Watchdog timer0x4000.0FFF0x4000.0000
-Reserved0x4000.3FFF0x4000.1000
155GPIO Port A0x4000.4FFF0x4000.4000
155GPIO Port B0x4000.5FFF0x4000.5000
155GPIO Port C0x4000.6FFF0x4000.6000
155GPIO Port D0x4000.7FFF0x4000.7000
302SSI00x4000.8FFF0x4000.8000
302SSI10x4000.9FFF0x4000.9000
-Reserved0x4000.BFFF0x4000.A000
257UART00x4000.CFFF0x4000.C000
-
Reserved0x4001.FFFF0x4000.D000
Peripherals
342I2C Master 00x4002.07FF0x4002.0000
355I2C Slave 00x4002.0FFF0x4002.0800
-Reserved0x4002.3FFF0x4002.1000
155GPIO Port E0x4002.4FFF0x4002.4000
155GPIO Port F0x4002.5FFF0x4002.5000
155GPIO Port G0x4002.6FFF0x4002.6000
-Reserved0x4002.FFFF0x4002.7000
201Timer00x4003.0FFF0x4003.0000
201Timer10x4003.1FFF0x4003.1000
201Timer20x4003.2FFF0x4003.2000
201Timer30x4003.3FFF0x4003.3000
-Reserved0x4003.FFFF0x4003.4000
384CAN0 Controller0x4004.0FFF0x4004.0000
June 22, 201046
Texas Instruments-Production Data
Memory Map