Register 15: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY layer. The default settings of
these registers are designed to initialize the Ethernet Controller to a normal operational mode without
configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
0123456789101112131415
reservedCOLTDUPLEXRANEGISOPWRDNANEGENSPEEDSLLOOPBKRESET
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000010001100Reset
DescriptionResetTypeNameBit/Field
Reset Registers
When set, this bit resets the PHY layer registers to their default state
and reinitializes internal state machines. Once the reset operation has
completed, this bit is cleared by hardware.
0R/WRESET15
Loopback Mode
When set, this bit enables the Loopback mode of operation. The receiver
ignores external inputs and receives the data that is transmitted by the
transmitter.
0R/WLOOPBK14
Speed Select
DescriptionValue
Enables the 100 Mb/s mode of operation (100BASE-TX).1
Enables the 10 Mb/s mode of operation (10BASE-T).0
1R/WSPEEDSL13
Auto-Negotiation Enable
When set, this bit enables the auto-negotiation process.
1R/WANEGEN12
Power Down
When set, this bit places the PHY layer into a low-power consuming
state. All data on the data inputs is ignored.
0R/WPWRDN11
Isolate
When set, this bit isolates the transmit and receive data paths and
ignores all data being transmitted and received.
0R/WISO10
Restart Auto-Negotiation
When set, this bit restarts the auto-negotiation process. Once the restart
has initiated, this bit is cleared by hardware.
0R/WRANEG9
441June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
