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LM3S8530-IQR80-C1

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型号: LM3S8530-IQR80-C1
PDF文件:
  • LM3S8530-IQR80-C1 PDF文件
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功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
PDF页面索引
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120%
DescriptionResetTypeNameBit/Field
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
0ROTXEMP2
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
The data length field stored in the TX FIFO exceeds 2032 decimal
(buffer length - 16 bytes of header data). The frame is not sent when
this error occurs.
The retransmission attempts during the backoff process have
exceeded the maximum limit of 16 decimal.
0ROTXER1
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
0RORXINT0
Writes
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type WO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTTXERTXEMPFOVRXERMDINTPHYINTreserved
W1CW1CW1CW1CW1CW1CW1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
Clear PHY Interrupt
Setting this bit clears the PHYINT interrupt in the MACRIS register.
0W1CPHYINT6
Clear MII Transaction Complete
Setting this bit clears the MDINT interrupt in the MACRIS register.
0W1CMDINT5
Clear Receive Error
Setting this bit clears the RXER interrupt in the MACRIS register.
0W1CRXER4
Clear FIFO Overrun
Setting this bit clears the FOV interrupt in the MACRIS register.
0W1CFOV3
June 22, 2010424
Texas Instruments-Production Data
Ethernet Controller
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