Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge
(MACRIS/MACIACK), offset 0x000
The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this
register gives the current status value of the corresponding interrupt prior to masking. On a write,
setting any bit clears the corresponding interrupt status bit.
Reads
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RXINTTXERTXEMPFOVRXERMDINTPHYINTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:7
PHY Interrupt
When set, indicates that an enabled interrupt in the PHY layer has
occurred. MR17 in the PHY must be read to determine the specific PHY
event that triggered this interrupt.
0ROPHYINT6
MII Transaction Complete
When set, indicates that a transaction (read or write) on the MII interface
has completed successfully.
0ROMDINT5
Receive Error
This bit indicates that an error was encountered on the receiver. The
possible errors that can cause this interrupt bit to be set are:
■ A receive error occurs during the reception of a frame (100 Mb/s
only).
■ The frame is not an integer number of bytes (dribble bits) due to an
alignment error.
■ The CRC of the frame does not pass the FCS check.
■ The length/type field is inconsistent with the frame data size when
interpreted as a length field.
0RORXER4
FIFO Overrun
When set, indicates that an overrun was encountered on the receive
FIFO.
0ROFOV3
423June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller