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LM3S8530-IQR80-C1

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型号: LM3S8530-IQR80-C1
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  • LM3S8530-IQR80-C1 PDF文件
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功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
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120%
Table 15-1. TX & RX FIFO Organization (continued)
RX FIFO (Read)TX FIFO (Write)Word Bit FieldsFIFO Word Read/Write
Sequence
SA oct 17:03rd
SA oct 215:8
SA oct 323:16
SA oct 431:24
SA oct 57:04th
SA oct 615:8
Len/Type Most Significant Byte23:16
Len/Type Least Significant Byte31:24
data oct n7:05th to nth
data oct n+115:8
data oct n+223:16
data oct n+331:24
FCS 17:0last
FCS 215:8
FCS 323:16
FCS 431:24
Note: If the CRC bit in the MACTCTL register is clear, the FCS bytes must be written with the
correct CRC. If the CRCbit is set, the Ethernet Controller automatically writes the FCS bytes.
15.2.1.3 Ethernet Transmission Options
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
The Ethernet Controller automatically generates and inserts the Frame Check Sequence (FCS) at
the end of the transmit frame when the CRC bit in the MACTCTL register is set. However, for test
purposes, this feature can be disabled in order to generate a frame with an invalid CRC by clearing
the CRC bit.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller automatically pads the data section if the payload data section loaded
into the FIFO is less than the minimum 46 bytes when the PADEN bit in the MACTCTL register is
set. This feature can be disabled by clearing the PADEN bit.
The transmitter must be enabled by setting the TXEN bit in the TCTL register.
15.2.1.4 Ethernet Reception Options
The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should
first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL)
register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register.
The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case,
a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the
BADCRC bit in the MACRCTL register.
In normal operating mode, the receiver accepts only those frames that have a destination address
that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0)
June 22, 2010416
Texas Instruments-Production Data
Ethernet Controller
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