Figure 15-1. Ethernet Controller
ARM Cortex M3
Ethernet Controller
Media
Access
Controller
Physical
Layer Entity
MAC
(Layer 2)
PHY
(Layer 1)
RJ45
Magnetics
Figure 15-2 on page 413 shows more detail of the internal structure of the Ethernet Controller and
how the register set relates to various functions.
Figure 15-2. Ethernet Controller Block Diagram
MACRIS
MACIACK
MACIM
Interrupt
Control
MACRCTL
MACNP
Receive
Control
MACTCTL
MACTHR
MACTR
Transmit
Control
Transmit
FIFO
Receive
FIFO
MACIA0
MACIA1
Individual
Address
MACMCTL
MACMDV
MII
Control
MACDDATA
Data
Access
TXOP
TXON
RXIP
RXIN
MDIX
Clock
Reference
Transmit
Encoding
Pulse
Shaping
Receive
Decoding
Clock
Recovery
Auto
Negotiation
Carrier
Sense
MR3
MR0
MR1
MR2
MR4
Media Independent Interface
Management Register Set
MR5
MR18
MR6
MR16
MR17
MR19
MR23
MR24
Collision
Detect
XTALNPHY
XTALPPHY
LED0
LED1
MACMTXD
MACMRXD
Interrupt
15.2 Functional Description
Note: A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS
pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used.
The functional description of the Ethernet Controller is discussed in the following sections.
15.2.1 MAC Operation
The following sections decribe the operation of the MAC unit, including an overview of the Ethernet
frame format, the MAC layer FIFOs, Ethernet transmission and reception options, and LED indicators.
413June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller