1.4.5.2 Flash (see page 125)
The LM3S8530 Flash controller supports 96 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.6 Additional Features
1.4.6.1 Memory Map (see page 46)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S8530 controller can be found in “Memory Map” on page 46. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.6.2 JTAG TAP Controller (see page 51)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris
®
JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris
®
JTAG instructions select the Stellaris
®
TDO
outputs. The multiplexer is controlled by the Stellaris
®
JTAG controller, which has comprehensive
programming for the ARM, Stellaris
®
, and unimplemented JTAG instructions.
1.4.6.3 System Control and Clocks (see page 63)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 459
■ “Signal Tables” on page 461
June 22, 201038
Texas Instruments-Production Data
Architectural Overview
