Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued)
DescriptionI2CMCS[3:0]I2CMSA[0]Current
State
RUNSTARTSTOPACKR/S
RECEIVE operation with negative ACK (master remains
in Master Receive state).
1000XMaster
Receive
STOP condition (master goes to Idle state).
b
001XX
RECEIVE followed by STOP condition (master goes to
Idle state).
1010X
RECEIVE operation (master remains in Master Receive
state).
1001X
Illegal.1011X
Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
11001
Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
11101
Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
11011
Repeated START condition followed by SEND (master
goes to Master Transmit state).
110X0
Repeated START condition followed by SEND and STOP
condition (master goes to Idle state).
111X0
NOP.All other combinations not listed are non-operations.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
347June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
