Register 2: I
2
C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I
2
C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits. The STARTbit causes
the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I
2
C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed
(or aborted due an error), the interrupt pin becomes active and the data may be read from the
I2CMDR register. When the I
2
C module operates in Master receiver mode, the ACK bit must be set
normally to logic 1. This causes the I
2
C bus controller to send an acknowledge automatically after
each byte. This bit must be reset when the I
2
C bus controller requires no further data to be sent
from the slave transmitter.
Reads
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BUSYERRORADRACKDATACKARBLSTIDLEBUSBSYreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:7
Bus Busy
This bit specifies the state of the I
2
C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START and
STOP conditions.
0ROBUSBSY6
I
2
C Idle
This bit specifies the I
2
C controller state. If set, the controller is idle;
otherwise the controller is not idle.
0ROIDLE5
Arbitration Lost
This bit specifies the result of bus arbitration. If set, the controller lost
arbitration; otherwise, the controller won arbitration.
0ROARBLST4
June 22, 2010344
Texas Instruments-Production Data
Inter-Integrated Circuit (I
2
C) Interface
