13.1 Block Diagram
Figure 13-1. I
2
C Block Diagram
I
2
C I/O Select
I
2
C Master Core
Interrupt
I
2
C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICRI2CMMIS
I
2
C Control
13.2 Functional Description
The I
2
C module is comprised of both master and slave functions which are implemented as separate
peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional
open-drain pads. A typical I
2
C bus configuration is shown in Figure 13-2 on page 329.
See “Inter-Integrated Circuit (I
2
C) Interface” on page 495 for I
2
C timing diagrams.
Figure 13-2. I
2
C Bus Configuration
R
PUP
Stellaris
TM
I2CSCL I2CSDA
R
PUP
3rd Party Device
with I
2
C Interface
SCL SDA
I
2
C Bus
SCL
SDA
3rd Party Device
with I
2
C Interface
SCL SDA
13.2.1 I
2
C Bus Functional Overview
The I
2
C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris
®
microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock
line. The bus is considered idle when both lines are High.
Every transaction on the I
2
C bus is nine bits long, consisting of eight data bits and a single
acknowledge bit. The number of bytes per transfer (defined as the time between a valid START
and STOP condition, described in “START and STOP Conditions” on page 330) is unrestricted, but
each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When
a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the
transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL.
329June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
