Register 6: SSI Interrupt Mask (SSIIM), offset 0x014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding
mask.
SSI Interrupt Mask (SSIIM)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x014
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
RORIMRTIMRXIMTXIMreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
SSI Transmit FIFO Interrupt Mask
The TXIM values are defined as follows:
DescriptionValue
TX FIFO half-full or less condition interrupt is masked.0
TX FIFO half-full or less condition interrupt is not masked.1
0R/WTXIM3
SSI Receive FIFO Interrupt Mask
The RXIM values are defined as follows:
DescriptionValue
RX FIFO half-full or more condition interrupt is masked.0
RX FIFO half-full or more condition interrupt is not masked.1
0R/WRXIM2
SSI Receive Time-Out Interrupt Mask
The RTIM values are defined as follows:
DescriptionValue
RX FIFO time-out interrupt is masked.0
RX FIFO time-out interrupt is not masked.1
0R/WRTIM1
311June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller