Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (on second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Watchdog Control (WDTCTL)
Base 0x4000.0000
Offset 0x008
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTENRESENreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:2
Watchdog Reset Enable
The RESEN values are defined as follows:
DescriptionValue
Disabled.0
Enable the Watchdog module reset output.1
0R/WRESEN1
Watchdog Interrupt Enable
The INTEN values are defined as follows:
DescriptionValue
Interrupt event disabled (once this bit is set, it can only be
cleared by a hardware reset).
0
Interrupt event enabled. Once enabled, all writes are ignored.1
0R/WINTEN0
June 22, 2010232
Texas Instruments-Production Data
Watchdog Timer