Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
GPTM TimerA Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TAMRTACMRTAAMSreserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:4
GPTM TimerA Alternate Mode Select
The TAAMS values are defined as follows:
DescriptionValue
Capture mode is enabled.0
PWM mode is enabled.1
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
0R/WTAAMS3
GPTM TimerA Capture Mode
The TACMR values are defined as follows:
DescriptionValue
Edge-Count mode0
Edge-Time mode1
0R/WTACMR2
203June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller