• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • LM3S8530-IQR80-C1 PDF文件及第159页内容在线浏览

LM3S8530-IQR80-C1

LM3S8530-IQR80-C1首页预览图
型号: LM3S8530-IQR80-C1
PDF文件:
  • LM3S8530-IQR80-C1 PDF文件
  • LM3S8530-IQR80-C1 PDF在线浏览
功能描述: Stellaris® LM3S8530 Microcontroller
PDF文件大小: 4249.13 Kbytes
PDF页数: 共526页
制造商: TI[Texas Instruments]
制造商LOGO: TI[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S8530-IQR80-C1
PDF页面索引
[1] 页[2] 页[3] 页[4] 页[5] 页[6] 页[7] 页[8] 页[9] 页[10] 页[11] 页[12] 页[13] 页[14] 页[15] 页[16] 页[17] 页[18] 页[19] 页[20] 页[21] 页[22] 页[23] 页[24] 页[25] 页[26] 页[27] 页[28] 页[29] 页[30] 页[31] 页[32] 页[33] 页[34] 页[35] 页[36] 页[37] 页[38] 页[39] 页[40] 页[41] 页[42] 页[43] 页[44] 页[45] 页[46] 页[47] 页[48] 页[49] 页[50] 页[51] 页[52] 页[53] 页[54] 页[55] 页[56] 页[57] 页[58] 页[59] 页[60] 页[61] 页[62] 页[63] 页[64] 页[65] 页[66] 页[67] 页[68] 页[69] 页[70] 页[71] 页[72] 页[73] 页[74] 页[75] 页[76] 页[77] 页[78] 页[79] 页[80] 页[81] 页[82] 页[83] 页[84] 页[85] 页[86] 页[87] 页[88] 页[89] 页[90] 页[91] 页[92] 页[93] 页[94] 页[95] 页[96] 页[97] 页[98] 页[99] 页[100] 页[101] 页[102] 页[103] 页[104] 页[105] 页[106] 页[107] 页[108] 页[109] 页[110] 页[111] 页[112] 页[113] 页[114] 页[115] 页[116] 页[117] 页[118] 页[119] 页[120] 页[121] 页[122] 页[123] 页[124] 页[125] 页[126] 页[127] 页[128] 页[129] 页[130] 页[131] 页[132] 页[133] 页[134] 页[135] 页[136] 页[137] 页[138] 页[139] 页[140] 页[141] 页[142] 页[143] 页[144] 页[145] 页[146] 页[147] 页[148] 页[149] 页[150] 页[151] 页[152] 页[153] 页[154] 页[155] 页[156] 页[157] 页[158] 页[159] 页[160] 页[161] 页[162] 页[163] 页[164] 页[165] 页[166] 页[167] 页[168] 页[169] 页[170] 页[171] 页[172] 页[173] 页[174] 页[175] 页[176] 页[177] 页[178] 页[179] 页[180] 页[181] 页[182] 页[183] 页[184] 页[185] 页[186] 页[187] 页[188] 页[189] 页[190] 页[191] 页[192] 页[193] 页[194] 页[195] 页[196] 页[197] 页[198] 页[199] 页[200] 页[201] 页[202] 页[203] 页[204] 页[205] 页[206] 页[207] 页[208] 页[209] 页[210] 页[211] 页[212] 页[213] 页[214] 页[215] 页[216] 页[217] 页[218] 页[219] 页[220] 页[221] 页[222] 页[223] 页[224] 页[225] 页[226] 页[227] 页[228] 页[229] 页[230] 页[231] 页[232] 页[233] 页[234] 页[235] 页[236] 页[237] 页[238] 页[239] 页[240] 页[241] 页[242] 页[243] 页[244] 页[245] 页[246] 页[247] 页[248] 页[249] 页[250] 页[251] 页[252] 页[253] 页[254] 页[255] 页[256] 页[257] 页[258] 页[259] 页[260] 页[261] 页[262] 页[263] 页[264] 页[265] 页[266] 页[267] 页[268] 页[269] 页[270] 页[271] 页[272] 页[273] 页[274] 页[275] 页[276] 页[277] 页[278] 页[279] 页[280] 页[281] 页[282] 页[283] 页[284] 页[285] 页[286] 页[287] 页[288] 页[289] 页[290] 页[291] 页[292] 页[293] 页[294] 页[295] 页[296] 页[297] 页[298] 页[299] 页[300] 页[301] 页[302] 页[303] 页[304] 页[305] 页[306] 页[307] 页[308] 页[309] 页[310] 页[311] 页[312] 页[313] 页[314] 页[315] 页[316] 页[317] 页[318] 页[319] 页[320] 页[321] 页[322] 页[323] 页[324] 页[325] 页[326] 页[327] 页[328] 页[329] 页[330] 页[331] 页[332] 页[333] 页[334] 页[335] 页[336] 页[337] 页[338] 页[339] 页[340] 页[341] 页[342] 页[343] 页[344] 页[345] 页[346] 页[347] 页[348] 页[349] 页[350] 页[351] 页[352] 页[353] 页[354] 页[355] 页[356] 页[357] 页[358] 页[359] 页[360] 页[361] 页[362] 页[363] 页[364] 页[365] 页[366] 页[367] 页[368] 页[369] 页[370] 页[371] 页[372] 页[373] 页[374] 页[375] 页[376] 页[377] 页[378] 页[379] 页[380] 页[381] 页[382] 页[383] 页[384] 页[385] 页[386] 页[387] 页[388] 页[389] 页[390] 页[391] 页[392] 页[393] 页[394] 页[395] 页[396] 页[397] 页[398] 页[399] 页[400] 页[401] 页[402] 页[403] 页[404] 页[405] 页[406] 页[407] 页[408] 页[409] 页[410] 页[411] 页[412] 页[413] 页[414] 页[415] 页[416] 页[417] 页[418] 页[419] 页[420] 页[421] 页[422] 页[423] 页[424] 页[425] 页[426] 页[427] 页[428] 页[429] 页[430] 页[431] 页[432] 页[433] 页[434] 页[435] 页[436] 页[437] 页[438] 页[439] 页[440] 页[441] 页[442] 页[443] 页[444] 页[445] 页[446] 页[447] 页[448] 页[449] 页[450] 页[451] 页[452] 页[453] 页[454] 页[455] 页[456] 页[457] 页[458] 页[459] 页[460] 页[461] 页[462] 页[463] 页[464] 页[465] 页[466] 页[467] 页[468] 页[469] 页[470] 页[471] 页[472] 页[473] 页[474] 页[475] 页[476] 页[477] 页[478] 页[479] 页[480] 页[481] 页[482] 页[483] 页[484] 页[485] 页[486] 页[487] 页[488] 页[489] 页[490] 页[491] 页[492] 页[493] 页[494] 页[495] 页[496] 页[497] 页[498] 页[499] 页[500] 页[501] 页[502] 页[503] 页[504] 页[505] 页[506] 页[507] 页[508] 页[509] 页[510] 页[511] 页[512] 页[513] 页[514] 页[515] 页[516] 页[517] 页[518] 页[519] 页[520] 页[521] 页[522] 页[523] 页[524] 页[525] 页[526] 页
120%
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 158) is set to detect edges, bits set to High in GPIOIBE
configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 160). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
GPIO Port F base: 0x4002.5000
GPIO Port G base: 0x4002.6000
Offset 0x408
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IBEreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:8
GPIO Interrupt Both Edges
The IBE values are defined as follows:
DescriptionValue
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 160).
0
Both edges on the corresponding pin trigger an interrupt.1
Note: Single edge is determined by the corresponding bit
in GPIOIEV.
0x00R/WIBE7:0
159June 22, 2010
Texas Instruments-Production Data
Stellaris® LM3S8530 Microcontroller
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价