Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 218
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 219
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 220
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 221
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 222
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 223
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 224
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 225
Watchdog Timer ........................................................................................................................... 226
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 230
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 231
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 232
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 233
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 234
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 235
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 236
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 237
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 238
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 239
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 240
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 241
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 242
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 243
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 244
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 245
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 246
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 247
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 248
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 249
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 250
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 258
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 260
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 262
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 264
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 265
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 266
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 267
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 269
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 271
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 273
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 275
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 276
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 277
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 279
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 280
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 281
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 282
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 283
June 22, 201014
Texas Instruments-Production Data
Table of Contents