Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
16171819202122232425262728293031
TIMER0TIMER1TIMER2TIMER3reserved
R/WR/WR/WR/WROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
UART0reservedSSI0SSI1reservedI2C0reserved
R/WROROROR/WR/WROROROROROROR/WROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:20
Timer 3 Reset Control
Reset control for General-Purpose Timer module 3.
0R/WTIMER319
Timer 2 Reset Control
Reset control for General-Purpose Timer module 2.
0R/WTIMER218
Timer 1 Reset Control
Reset control for General-Purpose Timer module 1.
0R/WTIMER117
Timer 0 Reset Control
Reset control for General-Purpose Timer module 0.
0R/WTIMER016
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved15:13
I2C0 Reset Control
Reset control for I2C unit 0.
0R/WI2C012
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved11:6
SSI1 Reset Control
Reset control for SSI unit 1.
0R/WSSI15
SSI0 Reset Control
Reset control for SSI unit 0.
0R/WSSI04
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved3:1
June 22, 2010120
Texas Instruments-Production Data
System Control