Table 23-14. Supported MOSC Crystal Frequencies (continued)
Crystal Frequency (MHz) Using the PLLCrystal Frequency (MHz) Not Using the PLL
4.9152 MHz
5 MHz
5.12 MHz
6 MHz (reset value)
6.144 MHz
7.3728 MHz
8 MHz
8.192 MHz
10.0 MHz
12.0 MHz
12.288 MHz
13.56 MHz
14.31818 MHz
16.0 MHz
16.384 MHz
23.8.6 System Clock Specification with ADC Operation
Table 23-15. System Clock Characteristics with ADC Operation
UnitMaxNomMinParameter NameParameter
MHz16.00481615.9952System clock frequency when the ADC
module is operating (when PLL is bypassed).
a
F
sysadc
a. Clock frequency (plus jitter) must be stable inside specified range. ADC can be clocked from the PLL or directly from an
external clock source, as long as frequency absolute precision is inside specified range.
23.9 Sleep Modes
Table 23-16. Sleep Modes AC Characteristics
a
UnitMaxNomMinParameter NameParameterParameter
No
system clocks2--Time to wake from interrupt in sleep mode, not
using the PLL
b
T
WAKE_S
D1
system clocks7--Time to wake from interrupt deep-sleep mode,
not using the PLL
b
T
WAKE_DS
msT
READY
--Time to wake from interrupt in sleep or
deep-sleep mode when using the PLL
b
T
WAKE_PLL_S
D2
ms35
c
0-Time to enter deep-sleep mode from sleep
request
T
ENTER_DS
D3
a. Values in this table assume the IOSC is the clock source during sleep or deep-sleep mode.
b. Specified from registering the interrupt to first instruction.
c. Nominal specification occurs 99.9995% of the time.
23.10 Hibernation Module
The Hibernation module requires special system implementation considerations because it is intended
to power down all other sections of its host device, refer to “Hibernation Module” on page 276.
989July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
