Table 21-2. Signals by Pin Number (continued)
DescriptionBuffer Type
a
Pin TypePin NamePin Number
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
TTLICMOD1
76
GPIO port C bit 3.TTLI/OPC3
77
JTAG TDO and SWO.TTLOSWO
JTAG TDO and SWO.TTLOTDO
GPIO port C bit 2.TTLI/OPC2
78
JTAG TDI.TTLITDI
GPIO port C bit 1.TTLI/OPC1
79
JTAG TMS and SWDIO.TTLI/OSWDIO
JTAG TMS and SWDIO.TTLITMS
GPIO port C bit 0.TTLI/OPC0
80
JTAG/SWD CLK.TTLISWCLK
JTAG/SWD CLK.TTLITCK
Positive supply for I/O and some logic.Power-VDD
81
Ground reference for logic and I/O pins.Power-GND
82
Positive supply for I/O and some logic.Power-VDD
83
Positive supply for I/O and some logic.Power-VDD
84
Ground reference for logic and I/O pins.Power-GND
85
Ground reference for logic and I/O pins.Power-GND
86
Ground reference for logic and I/O pins.Power-GND
87
Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 23-6 on page 986 .
Power-VDDC
88
GPIO port B bit 7.TTLI/OPB7
89
Non-maskable interrupt.TTLINMI
GPIO port B bit 6.TTLI/OPB6
90
Analog comparator 0 positive input.AnalogIC0+
Analog comparator 0 output.TTLOC0o
Capture/Compare/PWM 1.TTLI/OCCP1
Capture/Compare/PWM 5.TTLI/OCCP5
Capture/Compare/PWM 7.TTLI/OCCP7
PWM Fault 1.TTLIFault1
QEI module 0 index.TTLIIDX0
This input provides a reference voltage used to specify the input
voltage at which the ADC converts to a maximum value. In other
words, the voltage that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA input is limited
to the range specified in Table 23-22 on page 993 .
AnalogIVREFA
July 24, 2012932
Texas Instruments-Production Data
Signal Tables
OBSOLETE: TI has discontinued production of this device.
