Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. If a bit
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is R/W1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTINDEXINTTIMER
INTDIR
INTERROR
reserved
R/W1CR/W1CR/W1CR/W1CROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:4
Phase Error Interrupt
DescriptionValue
The INTERROR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
No interrupt has occurred or the interrupt is masked.0
This bit is cleared by writing a 1. Clearing this bit also clears the
INTERROR bit in the QEIRIS register.
0R/W1CINTERROR3
Direction Change Interrupt
DescriptionValue
The INTDIR bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
No interrupt has occurred or the interrupt is masked.0
This bit is cleared by writing a 1. Clearing this bit also clears the INTDIR
bit in the QEIRIS register.
0R/W1CINTDIR2
Velocity Timer Expired Interrupt
DescriptionValue
The INTTIMER bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
No interrupt has occurred or the interrupt is masked.0
This bit is cleared by writing a 1. Clearing this bit also clears the
INTTIMER bit in the QEIRIS register.
0R/W1CINTTIMER1
921July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.