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LM3S6G65-IQC80-A2T

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型号: LM3S6G65-IQC80-A2T
PDF文件:
  • LM3S6G65-IQC80-A2T PDF文件
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功能描述: Stellaris® LM3S6G65 Microcontroller
PDF文件大小: 6152.12 Kbytes
PDF页数: 共1044页
制造商: TI1[Texas Instruments]
制造商LOGO: TI1[Texas Instruments] LOGO
制造商网址: http://www.ti.com
捡单宝LM3S6G65-IQC80-A2T
PDF页面索引
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120%
Register 67: PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808
Register 68: PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888
Register 69: PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908
Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition
inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register
are read-only (RO) and provide the current state of the digital comparator triggers.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are
read / write 1 to clear (R/W1C) and provide a latched version of the digital comparator triggers. In
this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can
only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register
is set).
PWM0 Fault Status 1 (PWM0FLTSTAT1)
PWM0 base: 0x4002.8000
Offset 0x808
Type -, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DCMP0DCMP1DCMP2DCMP3DCMP4DCMP5DCMP6DCMP7reserved
--------ROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
Digital Comparator 7 Trigger
If the PWMnCTL register LATCH bit is clear, this bit represents the
current state of the Digital Comparator 7 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky
version of the trigger.
If DCMP7 is set, the trigger transitioned to the active state previously.
If DCMP7 is clear, the trigger has not transitioned to the active state
since the last time it was cleared.
The DCMP7 bit is cleared by writing it with the value 1.
0-DCMP77
897July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
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