Register 54: PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
Register 55: PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
Register 56: PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
This register specifies which digital comparator triggers from the ADC are used to generate a fault
condition. Each bit in the following register indicates whether the corresponding digital comparator
trigger is included in the fault condition. All enabled digital comparator triggers are ORed together
to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is
then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM
generator.
If the FLTSRCbit in the PWMnCTL register (see page 863) is clear, only the PWM Fault0pin affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWM0 Fault Source 1 (PWM0FLTSRC1)
PWM0 base: 0x4002.8000
Offset 0x078
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
DCMP0DCMP1DCMP2DCMP3DCMP4DCMP5DCMP6DCMP7reserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00ROreserved31:8
Digital Comparator 7
DescriptionValue
The trigger from digital comparator 7 is suppressed and cannot
generate a fault condition.
0
The trigger from digital comparator 7 is ORed with all other fault
condition generation inputs (Faultn signals and digital
comparators).
1
Note: The FLTSRCbit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
0R/WDCMP77
July 24, 2012890
Texas Instruments-Production Data
Pulse Width Modulator (PWM)
OBSOLETE: TI has discontinued production of this device.