Register 21: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 22: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 23: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the interrupt controller
(PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred
and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not
enabled. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt
reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
PWM0 base: 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
INTCNTZEROINTCNTLOAD
INTCMPAUINTCMPADINTCMPBUINTCMPBD
reserved
R/W1CR/W1CR/W1CR/W1CR/W1CR/W1CROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:6
Comparator B Down Interrupt
DescriptionValue
The INTCMPBDbits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
1
No interrupt has occurred or the interrupt is masked.0
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBD bit in the PWMnRIS register.
0R/W1CINTCMPBD5
Comparator B Up Interrupt
DescriptionValue
The INTCMPBUbits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
1
No interrupt has occurred or the interrupt is masked.0
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBU bit in the PWMnRIS register.
0R/W1CINTCMPBU4
873July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.