and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction
signal. These qualified pulses are used in the PWM generation process. If either comparator match
value is greater than the counter load value, then that comparator never outputs a High pulse.
Figure 18-3 on page 833 shows the behavior of the counter and the relationship of these pulses
when the counter is in Count-Down mode. Figure 18-4 on page 834 shows the behavior of the counter
and the relationship of these pulses when the counter is in Count-Up/Down mode. In these figures,
the following definitions apply:
■ LOAD is the value in the PWMnLOAD register
■ COMPA is the value in the PWMnCMPA register
■ COMPB is the value in the PWMnCMPB register
■ 0 is the value zero
■ load is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to the load value
■ zero is the internal signal that has a single-clock-cycle-width High pulse when the counter is zero
■ cmpA is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPA
■ cmpB is the internal signal that has a single-clock-cycle-width High pulse when the counter is
equal to COMPB
■ dir is the internal signal that indicates the count direction
Figure 18-3. PWM Count-Down Mode
LOAD
0
COMPB
COMPA
load
zero
cmpB
cmpA
dir
ADown
BDown
833July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.
