Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
IN0IN1reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000ROreserved31:2
Comparator 1 Interrupt Status
DescriptionValue
Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
1
An interrupt has not occurred.0
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
0ROIN11
Comparator 0 Interrupt Status
DescriptionValue
Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
1
An interrupt has not occurred.0
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
0ROIN00
July 24, 2012822
Texas Instruments-Production Data
Analog Comparators
OBSOLETE: TI has discontinued production of this device.