Table 2-8 on page 84 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 44 interrupts (listed in Table 2-9 on page 84).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 98.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 98 for more information on exceptions
and interrupts.
2.5.1 Exception States
Each exception is in one of the following states:
■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2 Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
July 24, 201282
Texas Instruments-Production Data
The Cortex-M3 Processor
OBSOLETE: TI has discontinued production of this device.
