Register 28: Ethernet PHY Management Register 30 – Interrupt Mask (MR30),
address 0x1E
This register enables interrupts to be generated by the various sources of PHY layer interrupts.
Ethernet PHY Management Register 30 – Interrupt Mask (MR30)
Base 0x4004.8000
Address 0x1E
Type R/W, reset 0x0000
0123456789101112131415
reserved
PRXIMPDFIMLPACKIMLDIMRFLTIM
ANCOMPIM
EONIMreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved15:8
ENERGYON Interrupt Enabled
DescriptionValue
An interrupt is sent to the interrupt controller when the EONIS
bit in the MR29 register is set.
1
The EONIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WEONIM7
Auto-Negotiation Complete Interrupt Enabled
DescriptionValue
An interrupt is sent to the interrupt controller when the
ANCOMPIS bit in the MR29 register is set.
1
The ANCOMPIS interrupt is suppressed and not sent to the
interrupt controller.
0
0R/WANCOMPIM6
Remote Fault Interrupt Enabled
DescriptionValue
An interrupt is sent to the interrupt controller when the RFLTIS
bit in the MR29 register is set.
1
The RFLTIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WRFLTIM5
Link Down Interrupt Enabled
DescriptionValue
An interrupt is sent to the interrupt controller when the LDIS bit
in the MR29 register is set.
1
The LDIS interrupt is suppressed and not sent to the interrupt
controller.
0
0R/WLDIM4
813July 24, 2012
Texas Instruments-Production Data
Stellaris
®
LM3S6G65 Microcontroller
OBSOLETE: TI has discontinued production of this device.